verilog: fix $past's signedness
authorJannis Harder <me@jix.one>
Tue, 24 May 2022 15:18:53 +0000 (17:18 +0200)
committerZachary Snow <zachary.j.snow@gmail.com>
Wed, 25 May 2022 20:32:08 +0000 (16:32 -0400)
commitb75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48
tree3b14fe3f5d0ace0370c49b56d77fb9b2ee458f80
parent63c9c9be5c0b0cc2b7f4588f1ac8e72eabc6bd0a
verilog: fix $past's signedness
CHANGELOG
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
tests/verilog/past_signedness.ys [new file with mode: 0644]