intel/disasm: Fix decoding of src0 of SENDS
authorJason Ekstrand <jason@jlekstrand.net>
Tue, 7 Jan 2020 04:14:29 +0000 (22:14 -0600)
committerJason Ekstrand <jason@jlekstrand.net>
Wed, 8 Jan 2020 14:14:16 +0000 (14:14 +0000)
commitb788cccfe2ff2b6897b73bbfe7e90e84899adec0
treed768d0cb0680e9d6c78923110be1b5ce37b8fc0c
parent8dcff01c8b7f0faf562a1f324d408869526995e4
intel/disasm: Fix decoding of src0 of SENDS

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
src/intel/compiler/brw_disasm.c