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(parent: 646d3b1) | patch
gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 2 Dec 2015 11:37:53 +0000 (12:37 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 2 Dec 2015 13:16:23 +0000 (14:16 +0100)
commitb7a1888a36d4b6457268cb6d5a4cb4edb8859b86
tree1c0bde86feb88b8914485bacf80e7a0c0a5a2956tree
parent646d3b19b4c092986d58a3016c7a5df2af278455commit | diff
gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus)

We will remove that when we will be using new migen simulator
litex/gen/fhdl/verilog.py diff | blob | history
litex/gen/sim/generic.py diff | blob | history
litex/soc/integration/builder.py diff | blob | history