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(parent: 4324c6f) | patch
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 12 Mar 2018 08:33:05 +0000 (09:33 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 12 Mar 2018 08:33:05 +0000 (09:33 +0100)
commitb7f7c8d159a53be0dbb713b86c658c3b79e023cb
treefb37827cfc191bb647013b7cb601a5527b9bfbf6tree
parent4324c6f666a48bd631443bb28958895f015223b8commit | diff
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
litex/build/xilinx/common.py diff | blob | history