sim: Move the draining interface into a separate base class
authorAndreas Sandberg <Andreas.Sandberg@arm.com>
Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)
committerAndreas Sandberg <Andreas.Sandberg@arm.com>
Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)
commitb81a977e6ab7dbfd122cb778cfe3d40ca7451198
tree09804c27367de8cf93623ec4644bf47abf316bf9
parenteb703a4b4e167e4d45f92203a1e0849f19cdba6d
sim: Move the draining interface into a separate base class

This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.
64 files changed:
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/simple/atomic.cc
src/cpu/simple/atomic.hh
src/cpu/simple/timing.cc
src/cpu/simple/timing.hh
src/cpu/testers/traffic_gen/traffic_gen.cc
src/cpu/testers/traffic_gen/traffic_gen.hh
src/dev/copy_engine.cc
src/dev/copy_engine.hh
src/dev/dma_device.cc
src/dev/dma_device.hh
src/dev/i8254xGBe.cc
src/dev/i8254xGBe.hh
src/dev/ide_disk.cc
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/ns_gige.cc
src/dev/ns_gige.hh
src/dev/pcidev.cc
src/dev/pcidev.hh
src/dev/sinic.cc
src/dev/sinic.hh
src/mem/bus.cc
src/mem/bus.hh
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/coherent_bus.cc
src/mem/coherent_bus.hh
src/mem/noncoherent_bus.cc
src/mem/noncoherent_bus.hh
src/mem/packet_queue.cc
src/mem/packet_queue.hh
src/mem/qport.hh
src/mem/ruby/system/MemoryControl.hh
src/mem/ruby/system/RubyMemoryControl.cc
src/mem/ruby/system/RubyMemoryControl.hh
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/ruby/system/Sequencer.cc
src/mem/simple_dram.cc
src/mem/simple_dram.hh
src/mem/simple_mem.cc
src/mem/simple_mem.hh
src/python/SConscript
src/python/m5/SimObject.py
src/python/m5/__init__.py
src/python/m5/internal/__init__.py
src/python/m5/simulate.py
src/python/swig/drain.i [new file with mode: 0644]
src/python/swig/event.i
src/python/swig/pyevent.cc
src/python/swig/pyevent.hh
src/sim/SConscript
src/sim/drain.cc [new file with mode: 0644]
src/sim/drain.hh [new file with mode: 0644]
src/sim/serialize.hh
src/sim/sim_events.cc
src/sim/sim_object.cc
src/sim/sim_object.hh
src/sim/system.cc
src/sim/system.hh