Add some different parameters. The main change is that the writeback count is now...
authorKevin Lim <ktlim@umich.edu>
Wed, 5 Jul 2006 19:51:36 +0000 (15:51 -0400)
committerKevin Lim <ktlim@umich.edu>
Wed, 5 Jul 2006 19:51:36 +0000 (15:51 -0400)
commitb84103811df3d0203cdde8524cdcce57ded706be
tree5c46ba1d284e178bf224d22242ce3ada029b3244
parent0fbecab797ffe7fc68e3a9af9fd0a21df37ec635
Add some different parameters.  The main change is that the writeback count is now limited so that it doesn't overflow the buffer.

src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
    Add in dispatchWidth, wbWidth, wbDepth parameters.  wbDepth is the number of cycles of wbWidth instructions that can be buffered.
src/cpu/o3/iew.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.  The IQ must make sure with the IEW stage that it can issue instructions prior to issuing.
src/cpu/o3/iew_impl.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.
src/cpu/o3/inst_queue_impl.hh:
    IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to decrement the writeback counter if there's a squashed load that returned.
src/python/m5/objects/AlphaO3CPU.py:
    Change the parameters to include dispatch width, writeback width, and writeback depth.

--HG--
extra : convert_revision : 31c8cc495273e3c481b79055562fc40f71291fc4
src/cpu/o3/alpha_cpu_builder.cc
src/cpu/o3/alpha_params.hh
src/cpu/o3/iew.hh
src/cpu/o3/iew_impl.hh
src/cpu/o3/inst_queue_impl.hh
src/cpu/o3/lsq_unit_impl.hh
src/python/m5/objects/AlphaO3CPU.py