correct wire declaration grammar for #1614
authorStefan Biereigel <stefan@biereigel.de>
Mon, 3 Feb 2020 20:29:40 +0000 (21:29 +0100)
committerStefan Biereigel <stefan@biereigel.de>
Mon, 3 Feb 2020 20:29:40 +0000 (21:29 +0100)
commitb844b078db0c8b61758c562fbb8324bd5013bfa1
tree800d3de125e0b2197799852931dce54a6cb919b0
parent60876ce183ee5f3980c378e190d996453d59a780
correct wire declaration grammar for #1614
frontends/verilog/verilog_parser.y