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(parent: 10c3da8) | patch
cores.pll: add PLL generators for Lattice ECP5 and Xilinx 7 Series.
authorJean-François Nguyen <jf@lambdaconcept.com>
Fri, 29 Oct 2021 14:41:22 +0000 (16:41 +0200)
committerJean-François Nguyen <jf@lambdaconcept.com>
Fri, 29 Oct 2021 14:43:01 +0000 (16:43 +0200)
commitb8625215e051f1df1ff02ee6ccf8e0a0bd400422
treefbb49177f0dbd25e95b357c6995aa0be8531387btree
parent10c3da8118d045de61c0db4acff1fb1e1631fecccommit | diff
cores.pll: add PLL generators for Lattice ECP5 and Xilinx 7 Series.
lambdasoc/cores/pll/__init__.py [new file with mode: 0644] blob
lambdasoc/cores/pll/lattice_ecp5.py [new file with mode: 0644] blob
lambdasoc/cores/pll/xilinx_7series.py [new file with mode: 0644] blob
lambdasoc/test/test_cores_pll_lattice_ecp5.py [new file with mode: 0644] blob
lambdasoc/test/test_cores_pll_xilinx_7series.py [new file with mode: 0644] blob