mem: Add tWR to DRAM activate and precharge constraints
authorAndreas Hansson <andreas.hansson@arm.com>
Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)
commitb8631d9ae8a1f9c478ad81c7cc23304b4a7ca919
tree802f928c1e7a04b7ad9288d037ee455b595a7aef
parentc735ef6cb08f109a614383e12f9f55148bcf0257
mem: Add tWR to DRAM activate and precharge constraints

This patch adds the write recovery time to the DRAM timing
constraints, and changes the current tRASDoneAt to a more generic
preAllowedAt, capturing when a precharge is allowed to take place.

The part of the DRAM access code that accounts for the precharge and
activate constraints is updated accordingly.
src/mem/DRAMCtrl.py
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh