misc: Update attribute syntax, and reorganize compiler.hh.
authorGabe Black <gabeblack@google.com>
Sun, 27 Sep 2020 01:26:02 +0000 (18:26 -0700)
committerGabe Black <gabeblack@google.com>
Mon, 28 Sep 2020 21:52:59 +0000 (21:52 +0000)
commitb877efa6d446aef16230fd0853675f41e5176379
treeb8bbdcb6a30e37976a0e212a37a70259501ae166
parent3c31a214b68c3bab41341708dad1c972ea3f5a77
misc: Update attribute syntax, and reorganize compiler.hh.

This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
78 files changed:
src/arch/arm/faults.cc
src/arch/arm/insts/macromem.cc
src/arch/arm/isa/insts/data64.isa
src/arch/arm/isa/insts/fp.isa
src/arch/arm/isa/insts/ldr64.isa
src/arch/arm/isa/insts/misc64.isa
src/arch/arm/isa/insts/sve.isa
src/arch/arm/isa/templates/mem.isa
src/arch/arm/isa/templates/sve_mem.isa
src/arch/arm/remote_gdb.hh
src/arch/arm/tlb.cc
src/arch/isa_parser.py
src/arch/mips/interrupts.cc
src/arch/mips/isa/formats/mem.isa
src/arch/mips/isa/formats/mt.isa
src/arch/power/isa/formats/mem.isa
src/arch/riscv/isa.cc
src/arch/sparc/isa/formats/basic.isa
src/arch/x86/isa/microops/regop.isa
src/arch/x86/ldstflags.hh
src/base/bmpwriter.hh
src/base/compiler.hh
src/base/loader/elf_object.cc
src/base/pngwriter.hh
src/base/stats/group.cc
src/base/vnc/vncinput.hh
src/base/vnc/vncserver.cc
src/base/vnc/vncserver.hh
src/cpu/kvm/x86_cpu.cc
src/cpu/minor/fetch1.cc
src/cpu/minor/lsq.cc
src/cpu/o3/commit_impl.hh
src/cpu/o3/lsq_impl.hh
src/cpu/o3/mem_dep_unit_impl.hh
src/cpu/o3/scoreboard.hh
src/cpu/pred/bpred_unit.cc
src/cpu/simple/timing.cc
src/cpu/testers/memtest/memtest.cc
src/cpu/trace/trace_cpu.cc
src/dev/arm/gic_v2.cc
src/dev/arm/smmu_v3_transl.hh
src/dev/hsa/hsa_packet_processor.cc
src/dev/hsa/hw_scheduler.cc
src/dev/net/sinic.cc
src/dev/net/tcp_iface.cc
src/dev/pci/copy_engine.cc
src/dev/virtio/base.hh
src/dev/virtio/block.hh
src/dev/virtio/console.hh
src/dev/virtio/fs9p.hh
src/dev/virtio/pci.cc
src/gpu-compute/compute_unit.cc
src/gpu-compute/schedule_stage.cc
src/kern/linux/helpers.cc
src/kern/linux/linux.cc
src/kern/system_events.cc
src/learning_gem5/part2/simple_cache.cc
src/mem/cache/base.cc
src/mem/cache/cache.cc
src/mem/cache/tags/fa_lru.cc
src/mem/coherent_xbar.cc
src/mem/dramsim2_wrapper.cc
src/mem/dramsim3_wrapper.cc
src/mem/external_slave.cc
src/mem/mem_interface.hh
src/mem/page_table.cc
src/mem/ruby/network/garnet/GarnetNetwork.cc
src/mem/ruby/network/garnet/OutputUnit.hh
src/mem/ruby/network/garnet/RoutingUnit.cc
src/mem/ruby/structures/CacheMemory.cc
src/mem/ruby/structures/PerfectCacheMemory.hh
src/mem/ruby/system/GPUCoalescer.cc
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubySystem.cc
src/mem/slicc/ast/PeekStatementAST.py
src/mem/slicc/symbols/StateMachine.py
src/sim/probe/probe.hh
src/sim/system.cc