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litedram: Split L2 PLRU into storage and logic
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 19 Sep 2022 08:05:30 +0000 (18:05 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Mon, 19 Sep 2022 08:05:30 +0000 (18:05 +1000)
commitb8f9c833f85a13514f61b64895fa9ae6f7c2d671
tree872f4dfdb4de9e278714e62bf5ba308a0235087ftree
parenta1f58679197fee9a8036539be585414ba0ee57dfcommit | diff
litedram: Split L2 PLRU into storage and logic

As has been done for the L1 dcache and icache, this puts the L2 cache
PLRU state into a little RAM and has a single copy of the logic to
calculate the pseudo-LRU way and update the PLRU state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
litedram/extras/litedram-wrapper-l2.vhdl diff | blob | history