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(parent: f7468f5) | patch
wowser, complex. implementing maddedu implicit RC/RS rules.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 13:59:45 +0000 (14:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 13:59:45 +0000 (14:59 +0100)
commitb90eb527783f7d39795be58ca59f40513edb01ca
tree02ef6c8f71362ca8a74d84de833295cd045f2906tree
parentf7468f57cdabc5685feaf503f4a5f9b669a35de7commit | diff
wowser, complex. implementing maddedu implicit RC/RS rules.
still TODO
    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
actually it is currently "if RC is scalar then RS=RC" which is more
sensible
src/openpower/decoder/power_decoder2.py diff | blob | history