more work on verilator backport
authorTobias Platen <tplaten@posteo.de>
Sun, 27 Mar 2022 17:33:39 +0000 (19:33 +0200)
committerTobias Platen <tplaten@posteo.de>
Sun, 27 Mar 2022 17:33:39 +0000 (19:33 +0200)
commitb9186b8d735f468e75ad8487a73c5e0048c39d81
treebfe6929f54c9151136612176e29d58affad9dad7
parentab2c64fa1c73c7669295f8296e69383e3c09f50d
more work on verilator backport
Makefile
fpga/top-generic.vhdl
soc.vhdl
verilator/microwatt-verilator.cpp
wishbone_bram_wrapper.vhdl