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(parent: a9ab6e2) | patch
sim: riscv: new port
authorMike Frysinger <vapier@gentoo.org>
Thu, 21 May 2015 15:16:45 +0000 (23:16 +0800)
committerMike Frysinger <vapier@gentoo.org>
Fri, 5 Feb 2021 00:02:19 +0000 (19:02 -0500)
commitb9249c461c72b35dd9b6f274406c336f6a68ae98
tree2f2314445c8c95e8dc1c3c8de6d824e9042b15fetree
parenta9ab6e2ea07829d89b97d1f47ecb524c251252e7commit | diff
sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
23 files changed:
sim/ChangeLog diff | blob | history
sim/common/ChangeLog diff | blob | history
sim/common/gennltvals.py diff | blob | history
sim/common/nltvals.def diff | blob | history
sim/configure diff | blob | history
sim/configure.tgt diff | blob | history
sim/riscv/ChangeLog [new file with mode: 0644] blob
sim/riscv/Makefile.in [new file with mode: 0644] blob
sim/riscv/aclocal.m4 [new file with mode: 0644] blob
sim/riscv/config.in [new file with mode: 0644] blob
sim/riscv/configure [new file with mode: 0755] blob
sim/riscv/configure.ac [new file with mode: 0644] blob
sim/riscv/interp.c [new file with mode: 0644] blob
sim/riscv/machs.c [new file with mode: 0644] blob
sim/riscv/machs.h [new file with mode: 0644] blob
sim/riscv/model_list.def [new file with mode: 0644] blob
sim/riscv/sim-main.c [new file with mode: 0644] blob
sim/riscv/sim-main.h [new file with mode: 0644] blob
sim/testsuite/ChangeLog diff | blob | history
sim/testsuite/riscv/ChangeLog [new file with mode: 0644] blob
sim/testsuite/riscv/allinsn.exp [new file with mode: 0644] blob
sim/testsuite/riscv/pass.s [new file with mode: 0644] blob
sim/testsuite/riscv/testutils.inc [new file with mode: 0644] blob