MIPS/opcodes: Disassemble the RFE instruction
authorMaciej W. Rozycki <macro@orcam.me.uk>
Sat, 29 May 2021 01:26:32 +0000 (03:26 +0200)
committerMaciej W. Rozycki <macro@orcam.me.uk>
Sat, 29 May 2021 01:26:32 +0000 (03:26 +0200)
commitb930964c425533f2344c6b26d4af17200bb42928
tree949f69c94cfa475f597e0cd80128fb7fe13f3f6b
parent21629cf8bc2b16d3c75dff0c3f1222b714bf90c2
MIPS/opcodes: Disassemble the RFE instruction

Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.

It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:

  00: 42000010  c0 0x10

to be produced rather than:

  00: 42000010  rfe

even for ISA levels that do include the RFE instruction.

Move the "rfe" entry ahead of "c0" then, correcting the problem.  Add a
suitable test case.

opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".

gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
gas/ChangeLog
gas/testsuite/gas/mips/mips.exp
gas/testsuite/gas/mips/rfe.d [new file with mode: 0644]
gas/testsuite/gas/mips/rfe.s [new file with mode: 0644]
opcodes/ChangeLog
opcodes/mips-opc.c