mem: Remove redundant is_top_level cache parameter
authorAndreas Hansson <andreas.hansson@arm.com>
Fri, 3 Jul 2015 14:14:43 +0000 (10:14 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Fri, 3 Jul 2015 14:14:43 +0000 (10:14 -0400)
commitb93c912013cd7f5417b92eaa33010af70e97f8ec
treee381afa1a581e3d676e9c91d9999c490fa6b1a23
parent71856cfbbcac94997839ac7831b3ac4b2ddf29a2
mem: Remove redundant is_top_level cache parameter

This patch takes the final step in removing the is_top_level parameter
from the cache. With the recent changes to read requests and write
invalidations, the parameter is no longer needed, and consequently
removed.

This also means that asymmetric cache hierarchies are now fully
supported (and we are actually using them already with L1 caches, but
no table-walker caches, connected to a shared L2).
configs/common/Caches.py
configs/common/O3_ARM_v7a.py
configs/example/memcheck.py
configs/example/memtest.py
src/mem/cache/BaseCache.py
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache_impl.hh