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(parent: f6e98e9) | patch
i965/cnl: Don't write to Cache Mode Register 1 on gen10+
authorAnuj Phogat <anuj.phogat@gmail.com>
Tue, 13 Jun 2017 21:22:06 +0000 (14:22 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Fri, 23 Jun 2017 18:16:00 +0000 (11:16 -0700)
commitb98055330932a19997e68f2c935b0c7dfd90d9c1
tree7d368f0e656f49c08ba3ae43a97dc9624d396912tree
parentf6e98e99e3e6d5755000761775dbf073f7c7a7f7commit | diff
i965/cnl: Don't write to Cache Mode Register 1 on gen10+

With below optimizations gone in gen10+ we have nothing left out to
write to CACHE_MODE_1:
Float Blend Optimization Enable: This bit have been removed in gen10+
Partial Resolve Disable in VC: Recommendation is to always set this
field to 0 in gen10+ and that's the default value of the bit.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_state_upload.c diff | blob | history