x86/Intel: improve diagnostics for ambiguous VCVT* operands
authorJan Beulich <jbeulich@suse.com>
Mon, 17 Feb 2020 07:56:18 +0000 (08:56 +0100)
committerJan Beulich <jbeulich@suse.com>
Mon, 17 Feb 2020 07:56:18 +0000 (08:56 +0100)
commitb9915cbc7d3ac2b9cd136248defbf9538b9a9bcf
treef99be238a8f95c1690e68193c96df0028da708ae
parentce504911e5c4068a3498eebde4064b24382c7598
x86/Intel: improve diagnostics for ambiguous VCVT* operands

Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.

For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
13 files changed:
gas/ChangeLog
gas/config/tc-i386.c
gas/testsuite/gas/i386/avx512dq-inval.l
gas/testsuite/gas/i386/avx512dq-inval.s
gas/testsuite/gas/i386/avx512vl-ambig.l [new file with mode: 0644]
gas/testsuite/gas/i386/avx512vl-ambig.s [new file with mode: 0644]
gas/testsuite/gas/i386/i386.exp
gas/testsuite/gas/i386/inval-avx.l
gas/testsuite/gas/i386/inval-avx512f.l
gas/testsuite/gas/i386/inval-avx512f.s
opcodes/ChangeLog
opcodes/i386-opc.tbl
opcodes/i386-tbl.h