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(parent: f916705) | patch
uart: Enable buffering the FIFO.
authorTim 'mithro' Ansell <me@mith.ro>
Sat, 27 Oct 2018 23:02:53 +0000 (16:02 -0700)
committerTim 'mithro' Ansell <me@mith.ro>
Sat, 27 Oct 2018 23:04:58 +0000 (16:04 -0700)
commitba0dd5728e04d4c24e67354304c70d29f96dfd20
treec74f7ac9e9f5f06234e65d5e6aa4a5f01cafad09tree
parentf916705313f6b556f66d931a0c2b0d5d18825f09commit | diff
uart: Enable buffering the FIFO.

On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
litex/soc/cores/uart.py diff | blob | history