git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <waterman@cs.berkeley.edu>
	Sat, 27 Sep 2014 18:01:22 +0000 (11:01 -0700)
committer	Andrew Waterman <waterman@cs.berkeley.edu>
	Sat, 27 Sep 2014 18:10:49 +0000 (11:10 -0700)
commit	baa8d8be1f1a3d83caf248533fda9abaa3b0ee70
tree	6fb99977824fefff067f34d7915fcefbc72e6043	tree
parent	eb27fce99c6f711a890c8647edaf077ec8d137d3	commit \| diff

Avoid use of __int128_t

It is nonstandard, and GCC doesn't support it on 32-bit platforms. The
resulting code for MULH[[S]U] is crappier, but that doesn't really matter,
as these instructions are dynamically infrequent.

hwacha/insn_template_hwacha_ut.h		diff \| blob \| history
riscv/cachesim.h		diff \| blob \| history
riscv/decode.h		diff \| blob \| history
riscv/dummy-rocc-test.c		diff \| blob \| history
riscv/insn_template.h		diff \| blob \| history
riscv/insns/mulh.h		diff \| blob \| history
riscv/insns/mulhsu.h		diff \| blob \| history
riscv/insns/mulhu.h		diff \| blob \| history
riscv/memtracer.h		diff \| blob \| history
riscv/mulhi.h	[new file with mode: 0644]	blob
riscv/riscv.mk.in		diff \| blob \| history

Simple-V augmented version of spike

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