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(parent: 84c54a1) | patch
add fpga/top-ulx3s.vhdl which sets dummy values for verilator signals
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 14:27:52 +0000 (14:27 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 14:27:52 +0000 (14:27 +0000)
commitbb16e1067261779414e2f64ada14b0d4d0a9a0f4
tree9d62481fa94203edd20bda566ddadbbd27fa8d3ctree
parent84c54a10f29f2b2f4b7246640b9aec68cb6cd94ecommit | diff
add fpga/top-ulx3s.vhdl which sets dummy values for verilator signals
this stops a whole batch of unnecessary debug signals going into
the nextpnr-ecp5 LPF constraints
Makefile diff | blob | history
fpga/top-ulx3s.vhdl [new file with mode: 0644] blob