hdl.cd: add negedge clock domains.
authorwhitequark <cz@m-labs.hk>
Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)
committerwhitequark <cz@m-labs.hk>
Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)
commitbb234498a88e5e989b90c3059a61136e455af286
treed72d153b57c0eb02e11f5f59b069ef1d0bdee8ab
parent5d174e4c3ce0a0602c432044d99e29f589616b35
hdl.cd: add negedge clock domains.

Fixes #185.
nmigen/back/pysim.py
nmigen/back/rtlil.py
nmigen/hdl/cd.py
nmigen/test/test_hdl_cd.py