[AArch64] Add SVE condition codes

[AArch64] Add SVE condition codes

SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST.  This patch adds support for these
names.

The patch also adds comments to the disassembly output to show the
alternative names of a condition code.  For example:

	cinv	x0, x1, cc

becomes:

     	cinv	x0, x1, cc  // cc = lo, ul, last

and:

	b.cc	f0 <...>

becomes:

     	b.cc	f0 <...>  // b.lo, b.ul, b.last

Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.

include/
	* opcode/aarch64.h (aarch64_cond): Bump array size to 4.

opcodes/
	* aarch64-dis.c (remove_dot_suffix): New function, split out from...
	(print_mnemonic_name): ...here.
	(print_comment): New function.
	(print_aarch64_insn): Call it.
	* aarch64-opc.c (aarch64_conds): Add SVE names.
	(aarch64_print_operand): Print alternative condition names in
	a comment.

gas/
	* config/tc-aarch64.c (opcode_lookup): Search for the end of
	a condition name, rather than assuming that it will have exactly
	2 characters.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/alias.d: Add new condition-code comments
	to the expected output.
	* testsuite/gas/aarch64/beq_1.d: Likewise.
	* testsuite/gas/aarch64/float-fp16.d: Likewise.
	* testsuite/gas/aarch64/int-insns.d: Likewise.
	* testsuite/gas/aarch64/no-aliases.d: Likewise.
	* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
	* testsuite/gas/aarch64/reloc-insn.d: Likewise.
	* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
	New test.

ld/
	* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
	* testsuite/ld-aarch64/weak-undefined.d: Likewise.