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(parent: 8c07e98) | patch
RISC-V/gas: allow generating up to 176-bit instructions with .insn
authorJan Beulich <jbeulich@suse.com>
Tue, 4 Oct 2022 07:46:11 +0000 (09:46 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 4 Oct 2022 07:46:11 +0000 (09:46 +0200)
commitbb996692bd9654d6f2345ab65742796d5fde6829
treeed55ad57f923ce14e22d3250d24971c80c453cd6tree
parent8c07e983a28cc05edb87882a33c072c0cdfdedc3commit | diff
RISC-V/gas: allow generating up to 176-bit instructions with .insn

For the time being simply utilize O_big to avoid widening other fields,
bypassing append_insn() etc.
gas/config/tc-riscv.c diff | blob | history
gas/testsuite/gas/riscv/insn-dwarf.d diff | blob | history
gas/testsuite/gas/riscv/insn-fail.l diff | blob | history
gas/testsuite/gas/riscv/insn-fail.s diff | blob | history
gas/testsuite/gas/riscv/insn-na.d diff | blob | history
gas/testsuite/gas/riscv/insn.d diff | blob | history
gas/testsuite/gas/riscv/insn.s diff | blob | history
include/opcode/riscv.h diff | blob | history