For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
authorAndrew Cagney <cagney@redhat.com>
Mon, 8 Dec 1997 03:22:58 +0000 (03:22 +0000)
committerAndrew Cagney <cagney@redhat.com>
Mon, 8 Dec 1997 03:22:58 +0000 (03:22 +0000)
commitbc6df23d1457c9c5e9616f737659d68d7fef6e50
tree939e443924f25f220bb46be291d4b15852230d73
parent0a5875fc63c256f0daa9db6ed9a35257ab3db247
For "trap", IBT and RIE exceptions, mask all PSW.SM.  NB: Stepping
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
sim/d10v/ChangeLog
sim/d10v/d10v_sim.h
sim/d10v/simops.c
sim/testsuite/d10v-elf/ChangeLog