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(parent: 29fee01) | patch
hdl.ast, back.rtlil: add source locations to anonymous wires.
authorwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 12:44:52 +0000 (12:44 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 12:51:57 +0000 (12:51 +0000)
commitbcdc280a873ad369077f446df025d09b28dbead9
treef6fddbc418bab9caa43f0e618ec7d18ffe559bcatree
parent29fee01f8629fcc10a0b52598d817f32e803bcb4commit | diff
hdl.ast, back.rtlil: add source locations to anonymous wires.

This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
nmigen/back/rtlil.py diff | blob | history
nmigen/hdl/ast.py diff | blob | history