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(parent: 9e01bf5) | patch
uart: create phy directory and move phy logic to serial.py (will enable selecting...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 10:58:46 +0000 (11:58 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 11:14:34 +0000 (12:14 +0100)
commitbd4d3cd73ba9d4033092d3bb77c42f1d75c2f8bf
tree093f6c663f7c327dc8ca78b8d117d65d4cdc3efftree
parent9e01bf5fdd139fb323cb1737cdb8c55b7f381689commit | diff
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
misoclib/com/uart/__init__.py diff | blob | history
misoclib/com/uart/phy/__init__.py [new file with mode: 0644] blob
misoclib/com/uart/phy/serial.py [new file with mode: 0644] blob
misoclib/com/uart/test/test_serial_phy.py [new file with mode: 0644] blob
misoclib/soc/__init__.py diff | blob | history
misoclib/soc/sdram.py diff | blob | history