i965: Don't set interleave or complete on TCS EOT message.
authorKenneth Graunke <kenneth@whitecape.org>
Thu, 24 Dec 2015 21:09:26 +0000 (13:09 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 28 Dec 2015 21:17:03 +0000 (13:17 -0800)
commitbd8ab8dedb2cc557ea3cb58d507f237743b3f7f9
tree4c5c4b0a081890f90920be3f0f89fa6151f0a141
parentb7793783b3df94880655234bc2a9054eddf01913
i965: Don't set interleave or complete on TCS EOT message.

Setting interleave on the TCS EOT message causes Ivybridge hardware to
GPU hang like crazy.  Individual tests would pass, but running even a
simple test like nop.shader_test in a loop would hang within 1-3 runs.
Adding sleep delays worked around the problem, somehow.

Interleave doesn't make much sense given that we only have one patch
URB handle, not two.  Complete doesn't seem useful either.

There's no reason to actually set those bits.  We were just being lazy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_shader.cpp
src/mesa/drivers/dri/i965/brw_vec4.cpp
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp