i965: Use ISL for emitting depth/stencil/hiz state on gen6+
authorJason Ekstrand <jason.ekstrand@intel.com>
Sat, 5 May 2018 05:32:24 +0000 (22:32 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Tue, 8 May 2018 15:27:44 +0000 (08:27 -0700)
commitbdbb527a65fc729e7a9319ae67de60d03d06c3fd
tree130ced88b4416251d9e77174a547431c302038ec
parentccd3dce3c059ad6d24ab50107ac6bb8827f46c3d
i965: Use ISL for emitting depth/stencil/hiz state on gen6+

We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5.  Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.

Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/Makefile.sources
src/mesa/drivers/dri/i965/brw_context.c
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_misc_state.c
src/mesa/drivers/dri/i965/brw_state.h
src/mesa/drivers/dri/i965/gen6_depth_state.c [deleted file]
src/mesa/drivers/dri/i965/gen7_misc_state.c [deleted file]
src/mesa/drivers/dri/i965/gen8_depth_state.c
src/mesa/drivers/dri/i965/meson.build