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(parent: 89fefef) | patch
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all...
authorSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 18 Mar 2015 11:08:25 +0000 (12:08 +0100)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 18 Mar 2015 11:08:25 +0000 (12:08 +0100)
commitbdc47b205ac3c9624f3e82d21ff88e9a5b383030
treed38e11bffeb1c5fc420bf83d885ab83529461b7ftree
parent89fefef3f8fc78b1fceefe93dcb3385efacdb79acommit | diff
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"

This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e4538277308e374cd1f0b1b9a31f66dc5a.
migen/fhdl/verilog.py diff | blob | history