inorder: pipe. stage inst. buffering
authorKorey Sewell <ksewell@umich.edu>
Fri, 4 Feb 2011 05:08:16 +0000 (00:08 -0500)
committerKorey Sewell <ksewell@umich.edu>
Fri, 4 Feb 2011 05:08:16 +0000 (00:08 -0500)
commitbe17617990ea2b95e0f08324570b2bbf93dee1f0
treecdfe04692ce59363c46a7aec13827f85a0366e0d
parent050944dd7388231a334b81adf65e535058cf13fb
inorder: pipe. stage inst. buffering
use skidbuffer as only location for instructions between stages. before,
we had the insts queue from the prior stage and the skidbuffer for the
current stage, but that gets confusing and this consolidation helps
when handling squash cases
src/cpu/inorder/first_stage.cc
src/cpu/inorder/first_stage.hh
src/cpu/inorder/pipeline_stage.cc
src/cpu/inorder/pipeline_stage.hh