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(parent: 242b4fb) | patch
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x
authorKito Cheng <kito.cheng@sifive.com>
Tue, 18 Feb 2020 05:47:50 +0000 (13:47 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 19 Feb 2020 05:03:51 +0000 (13:03 +0800)
commitbfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6
tree08b3bf5f5cc03b417b6ffc596ba93c0173404012tree
parent242b4fb7f4e6c6224e727fa5e9ed8a776d16ccf9commit | diff
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x

 - fmv.x.s/fmv.s.x renamed to fmv.x.w/fmv.w.x in the latest RISC-V ISA
   manual.

 - Tested rv32gc/rv64gc on bare-metal with qemu.

ChangeLog

gcc/

Kito Cheng  <kito.cheng@sifive.com>

* config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
rather than fmv.x.s/fmv.s.x.
gcc/ChangeLog diff | blob | history
gcc/config/riscv/riscv.c diff | blob | history