Removed RTLIL::SigSpec::optimize()
authorClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 18:32:28 +0000 (20:32 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 18:32:28 +0000 (20:32 +0200)
commitc094c53de83707a5bf1b268640283f1dde235873
tree27e480f63e0d34d8cbfcf8fcf29472c198381296
parent8fd8e4a468fb650fe5dcbe892c07010f627e2c2b
Removed RTLIL::SigSpec::optimize()
24 files changed:
backends/blif/blif.cc
backends/edif/edif.cc
backends/intersynth/intersynth.cc
backends/verilog/verilog_backend.cc
frontends/ast/genrtlil.cc
kernel/bitpattern.h
kernel/rtlil.cc
kernel/rtlil.h
passes/abc/blifparse.cc
passes/cmds/setundef.cc
passes/cmds/show.cc
passes/cmds/splice.cc
passes/cmds/splitnets.cc
passes/fsm/fsm_map.cc
passes/memory/memory_collect.cc
passes/memory/memory_dff.cc
passes/memory/memory_share.cc
passes/opt/opt_clean.cc
passes/opt/opt_const.cc
passes/proc/proc_dff.cc
passes/proc/proc_init.cc
passes/sat/eval.cc
passes/sat/freduce.cc
passes/sat/sat.cc