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(parent: 3c390c7) | patch
power: Added support for CR, XER, FPSR, MSR, PTCR Registers
authorPhanikiran Harithas <phanikiran.harithas@gmail.com>
Sun, 10 Jun 2018 08:19:58 +0000 (13:49 +0530)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 Jan 2021 03:50:26 +0000 (03:50 +0000)
commitc0a975496f76c8b901be8e7efb7e3cb3ae9cbdf5
treee0f9df6906cb24a06eb453c718fdd0d3a8a10b2dtree
parent3c390c71d8d6a5e38b656b892ea445bfee89ff0acommit | diff
power: Added support for CR, XER, FPSR, MSR, PTCR Registers

Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.

In particular, annotate the bits of MSR and PTCR for future use.

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608
src/arch/power/miscregs.hh diff | blob | history
src/arch/power/system.cc diff | blob | history