sim: Include object header files in SWIG interfaces
authorAndreas Sandberg <Andreas.Sandberg@arm.com>
Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)
committerAndreas Sandberg <Andreas.Sandberg@arm.com>
Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)
commitc0ab52799ca4ebd0a51363cfedd0658e6d79b842
treeafdf65e4593c64bbc1d5b511aacbaf0fa4b558ad
parent044a6525876efc61838dffa89ac52425d510b754
sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
122 files changed:
src/SConscript
src/arch/alpha/AlphaInterrupts.py
src/arch/alpha/AlphaSystem.py
src/arch/alpha/AlphaTLB.py
src/arch/arm/ArmInterrupts.py
src/arch/arm/ArmNativeTrace.py
src/arch/arm/ArmSystem.py
src/arch/arm/ArmTLB.py
src/arch/mips/MipsInterrupts.py
src/arch/mips/MipsSystem.py
src/arch/mips/MipsTLB.py
src/arch/power/PowerInterrupts.py
src/arch/power/PowerTLB.py
src/arch/sparc/SparcInterrupts.py
src/arch/sparc/SparcNativeTrace.py
src/arch/sparc/SparcSystem.py
src/arch/sparc/SparcTLB.py
src/arch/x86/X86LocalApic.py
src/arch/x86/X86NativeTrace.py
src/arch/x86/X86System.py
src/arch/x86/X86TLB.py
src/arch/x86/bios/ACPI.py
src/arch/x86/bios/E820.py
src/arch/x86/bios/IntelMP.py
src/arch/x86/bios/SMBios.py
src/base/CPA.py
src/base/vnc/Vnc.py
src/cpu/BaseCPU.py
src/cpu/CheckerCPU.py
src/cpu/ExeTracer.py
src/cpu/FuncUnit.py
src/cpu/IntelTrace.py
src/cpu/IntrControl.py
src/cpu/LegionTrace.py
src/cpu/NativeTrace.py
src/cpu/inorder/InOrderCPU.py
src/cpu/inorder/InOrderTrace.py
src/cpu/inteltrace.hh
src/cpu/o3/FUPool.py
src/cpu/simple/AtomicSimpleCPU.py
src/cpu/simple/BaseSimpleCPU.py
src/cpu/simple/TimingSimpleCPU.py
src/cpu/static_inst.hh
src/cpu/testers/directedtest/RubyDirectedTester.py
src/cpu/testers/memtest/MemTest.py
src/cpu/testers/networktest/NetworkTest.py
src/cpu/testers/rubytest/RubyTester.py
src/cpu/testers/traffic_gen/TrafficGen.py
src/dev/BadDevice.py
src/dev/CopyEngine.py
src/dev/Device.py
src/dev/DiskImage.py
src/dev/Ethernet.py
src/dev/Ide.py
src/dev/Pci.py
src/dev/Platform.py
src/dev/SimpleDisk.py
src/dev/Terminal.py
src/dev/Uart.py
src/dev/alpha/AlphaBackdoor.py
src/dev/alpha/Tsunami.py
src/dev/alpha/tsunami_io.hh
src/dev/arm/RealView.py
src/dev/arm/pl011.hh
src/dev/arm/realview.hh
src/dev/arm/timer_cpulocal.hh
src/dev/copy_engine.hh
src/dev/mips/Malta.py
src/dev/mips/malta_io.hh
src/dev/sparc/T1000.py
src/dev/x86/Cmos.py
src/dev/x86/I8042.py
src/dev/x86/I82094AA.py
src/dev/x86/I8237.py
src/dev/x86/I8254.py
src/dev/x86/I8259.py
src/dev/x86/Pc.py
src/dev/x86/PcSpeaker.py
src/dev/x86/SouthBridge.py
src/dev/x86/X86IntPin.py
src/dev/x86/speaker.hh
src/mem/AbstractMemory.py
src/mem/AddrMapper.py
src/mem/Bridge.py
src/mem/Bus.py
src/mem/CommMonitor.py
src/mem/MemObject.py
src/mem/SimpleDRAM.py
src/mem/SimpleMemory.py
src/mem/cache/BaseCache.py
src/mem/cache/prefetch/Prefetcher.py
src/mem/cache/tags/iic_repl/Repl.py
src/mem/ruby/network/BasicLink.py
src/mem/ruby/network/BasicRouter.py
src/mem/ruby/network/Network.py
src/mem/ruby/network/fault_model/FaultModel.py
src/mem/ruby/network/garnet/BaseGarnetNetwork.py
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
src/mem/ruby/network/simple/SimpleLink.py
src/mem/ruby/network/simple/SimpleNetwork.py
src/mem/ruby/profiler/Profiler.py
src/mem/ruby/slicc_interface/Controller.py
src/mem/ruby/system/Cache.py
src/mem/ruby/system/DirectoryMemory.py
src/mem/ruby/system/MemoryControl.py
src/mem/ruby/system/RubyMemoryControl.py
src/mem/ruby/system/RubySystem.py
src/mem/ruby/system/Sequencer.py
src/mem/ruby/system/WireBuffer.py
src/mem/slicc/symbols/StateMachine.py
src/python/m5/SimObject.py
src/sim/BaseTLB.py
src/sim/ClockedObject.py
src/sim/InstTracer.py
src/sim/Process.py
src/sim/Root.py
src/sim/System.py