pwr: Adds logic to enter power gating for the cpu model
authorAnouk Van Laer <anouk.vanlaer@arm.com>
Fri, 17 Mar 2017 12:02:00 +0000 (12:02 +0000)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Mon, 20 Nov 2017 11:03:03 +0000 (11:03 +0000)
commitc0d613adb4eca09c32aca1cc90f04c29574f69c6
tree1c2a0d26778d8b8ca3f0b359f990dc695156bf8f
parentd626f4f7aaa4d2c9f7ae1afc35577fa025b4de38
pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state.  This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/cpu/BaseCPU.py
src/cpu/base.cc
src/cpu/base.hh
src/cpu/minor/cpu.cc
src/cpu/o3/cpu.cc
src/cpu/simple/atomic.cc
src/cpu/simple/timing.cc