fhdl/verilog: change the way we initialize reg: reg name = init_value;
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 18 Mar 2015 14:04:58 +0000 (15:04 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 18 Mar 2015 14:05:26 +0000 (15:05 +0100)
commitc0fb0ef6002849f08c664b955cea8c557c7497e4
tree4168722511e683bcb0600de413c75f47499b7d54
parentea9c1b8e69a672b2bcdc8243a49ca7854f6c95b0
fhdl/verilog: change the way we initialize reg: reg name = init_value;
This allows simplifications (init in _printsync and _printinit no longer needed)
migen/fhdl/verilog.py