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(parent: d2cbc70) | patch
fhdl/verilog: insert reset before listing signals
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 27 Feb 2013 17:10:04 +0000 (18:10 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 27 Feb 2013 17:10:04 +0000 (18:10 +0100)
commitc10622f5e295ec69e7e687a6bc65db0cd8afbb96
treedee018fc499ae571ca40f4ef4dcd4925a60851fatree
parentd2cbc70190a7157f477a6b8b32a38c5603fb1df8commit | diff
fhdl/verilog: insert reset before listing signals
migen/fhdl/tools.py diff | blob | history
migen/fhdl/verilog.py diff | blob | history