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(parent: 7c611ef) | patch
in DCT/FFT 3-in 2-out set had to make RT same source-dest EXTRA
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 15 May 2023 15:07:04 +0000 (16:07 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:18 +0000 (19:51 +0100)
commitc11cc1ae4c5acfeb7b06c416a110f4f9eea16028
treeba2964e2abf9303be86c78d8ae667fa0d8010f6atree
parent7c611efabb861f3b9761f97120ade2a890da8cdfcommit | diff
in DCT/FFT 3-in 2-out set had to make RT same source-dest EXTRA
puzzlingly this frees up 2 bits but still cannot do EXTRA3 due to needing
1 bit for selecting RS=RT+MAXVL or RS=RC
openpower/isatables/RM-1P-3S1D.csv diff | blob | history
src/openpower/sv/sv_analysis.py diff | blob | history