add mode for half-swap, to be combined with LD-bit-reversed for loading DCT
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Jul 2021 11:16:18 +0000 (12:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Jul 2021 11:16:18 +0000 (12:16 +0100)
commitc14b2ceb27d446b088711a7a76f116c0a94534e4
tree5ba8964900d4ea13aea9ad87322e371e67c2edaa
parent033e2d6cfd0be4d9ec0623fa4f1c9c1965e36ebb
add mode for half-swap, to be combined with LD-bit-reversed for loading DCT
data
openpower/isa/simplev.mdwn
src/openpower/decoder/isa/remap_dct_yield.py
src/openpower/decoder/isa/svshape.py