aarch64: Add vector/vector vec_extract patterns [PR92822]

aarch64: Add vector/vector vec_extract patterns [PR92822]

Part of the problem in this PR is that we don't provide patterns
to extract a 64-bit vector from one half of a 128-bit vector.
Adding them fixes:

FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\td[0-9]+, d[0-9]+, d[0-9]+ 1
FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.d\\[[0-9]+\\] 3

The 2s failures need target-independent changes, after which they rely
on these patterns too.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/92822
	* config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
	expander.
	(@aarch64_split_simd_mov<mode>): Use it.
	(aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
	Leave the vec_extract patterns to handle 2-element vectors.
	(aarch64_simd_mov_from_<mode>high): Likewise.
	(vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
	(vec_extractv2dfv1df): Likewise.