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(parent: 7d2097b) | patch
verilog: impose limit on maximum expression width
authorZachary Snow <zach@zachjs.com>
Thu, 4 Mar 2021 20:08:16 +0000 (15:08 -0500)
committerZachary Snow <zach@zachjs.com>
Thu, 4 Mar 2021 20:20:52 +0000 (15:20 -0500)
commitc18ddbcd822410095d28c4be1c3ac3c6358622d2
tree405d9312fc0b723f0af7b730bece916fde66fc1atree
parent7d2097b00538fa366cc433b23c2c307db0e3a4becommit | diff
verilog: impose limit on maximum expression width

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
frontends/ast/genrtlil.cc diff | blob | history
tests/verilog/absurd_width.ys [new file with mode: 0644] blob
tests/verilog/absurd_width_const.ys [new file with mode: 0644] blob