RISC-V: Add macro-only operands to validate_riscv_insn
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sun, 7 Aug 2022 05:57:00 +0000 (14:57 +0900)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Thu, 22 Sep 2022 06:28:19 +0000 (06:28 +0000)
commitc1ecdee7e09681096229c177bb5fba8a538ce446
treece0f993e68b5bde0c2c36146331d0e791bc5ab5c
parent90eca7111355e4c6683c1ab10fd07107ea10f6d1
RISC-V: Add macro-only operands to validate_riscv_insn

Although they are not (and should not be) reachable, following macro-only
operands are parsed in the `validate_riscv_insn' function and ignored.
That function also notes that they are macro-only.

-   "A"
-   "B"
-   "I"

Following this convention, this commit adds three remaining macro-only
operands to this function.  By doing this, we could instead choose to reject
those operands from appearing in regular instructions later.

-   "c"   (used by call, tail and jump macros)
-   "VM"  (used by vmsge.vx and vmsgeu.vx macros)
-   "VT"  (likewise)

gas/ChangeLog:

* config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT"
macro-only operand types.
gas/config/tc-riscv.c