Fix SYNTHESIS always being defined in Verilog frontend
authorgeorgerennie <georgerennie@gmail.com>
Tue, 1 Dec 2020 01:37:19 +0000 (01:37 +0000)
committergeorgerennie <georgerennie@gmail.com>
Tue, 1 Dec 2020 01:37:19 +0000 (01:37 +0000)
commitc1f6ce8b33b1c06a4e38b621e27876d5715eb26d
treeef64f8bd35b8ed518ba347b91ef41494e4d15527
parent2116c585810cddb73777b46ea9aad0d6d511d82b
Fix SYNTHESIS always being defined in Verilog frontend
frontends/verilog/preproc.cc
frontends/verilog/verilog_frontend.cc