soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 15 Apr 2019 09:36:42 +0000 (11:36 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 15 Apr 2019 09:36:42 +0000 (11:36 +0200)
commitc252972bef8524ca167917270c78f1bbb9582aca
treefbb62eaa8e8d109c56fc799d83ab4694c2edf91c
parentf986974d608bae6f5e6fe09c260d8c93729c817c
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
litex/soc/cores/clock.py