projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 879478a) | patch
reorganize code
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 27 Sep 2014 13:34:28 +0000 (15:34 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 27 Sep 2014 13:34:28 +0000 (15:34 +0200)
commitc27f24c4c09f23157c5950a3fbddd7c0414de433
tree4cf283c24fd081af4902ed4010f1cfdb7a555519tree
parent879478a6e4ff6c8da5e56784b70aca6baeed057bcommit | diff
reorganize code
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
lib/sata/k7sataphy/__init__.py diff | blob | history
lib/sata/k7sataphy/clocking.py [deleted file] blob | history
lib/sata/k7sataphy/crg.py [new file with mode: 0644] blob
lib/sata/k7sataphy/ctrl.py diff | blob | history
lib/sata/k7sataphy/datapath.py [new file with mode: 0644] blob
lib/sata/k7sataphy/gtx.py diff | blob | history
targets/test.py diff | blob | history