projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c964c42) | patch
hdl.ir: when adding sync domain to a design, also add it to ports.
authorwhitequark <cz@m-labs.hk>
Wed, 15 May 2019 06:44:50 +0000 (06:44 +0000)
committerwhitequark <cz@m-labs.hk>
Wed, 15 May 2019 06:44:50 +0000 (06:44 +0000)
commitc2948277c0f2b5c9dc1656e41c4bbae54269b010
treedb90005d694322c340589d008f0f3f192e4a0c4dtree
parentc964c42d70d972342f61ac5b9bdc9ff6b4a606b5commit | diff
hdl.ir: when adding sync domain to a design, also add it to ports.

Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
nmigen/hdl/ir.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history