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(parent: 60c3ea3) | patch
anlogic: support BRAM mapping
authorIcenowy Zheng <icenowy@aosc.io>
Fri, 17 Dec 2021 12:25:32 +0000 (20:25 +0800)
committerIcenowy Zheng <icenowy@aosc.io>
Fri, 17 Dec 2021 12:28:22 +0000 (20:28 +0800)
commitc2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5
tree70021f14e73c9b9db20047caf7f4995855edbc2btree
parent60c3ea367c942459a95e610ed98f277ce46c0142commit | diff
anlogic: support BRAM mapping

Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
techlibs/anlogic/.gitignore [new file with mode: 0644] blob
techlibs/anlogic/Makefile.inc diff | blob | history
techlibs/anlogic/brams.txt [new file with mode: 0644] blob
techlibs/anlogic/brams_init.py [new file with mode: 0644] blob
techlibs/anlogic/brams_map.v [new file with mode: 0644] blob
techlibs/anlogic/synth_anlogic.cc diff | blob | history
tests/arch/anlogic/blockram.ys [new file with mode: 0644] blob
tests/arch/anlogic/lutram.ys diff | blob | history