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(parent: fa1577e) | patch
fix fcvttg FPSCR.FR computation
authorJacob Lifshay <programmerjake@gmail.com>
Fri, 19 May 2023 03:53:23 +0000 (20:53 -0700)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:18 +0000 (19:51 +0100)
commitc2c02f583403b8a168fa2374d4c65b9a832f7d23
treec463dbea660bc0306b4f78e1ce377b7b92b27786tree
parentfa1577ea8052e7f1d17a49e2ddd59cc644d9db2ccommit | diff
fix fcvttg FPSCR.FR computation

the unit test previously assumed the rounding mode is truncate,
but when I switched it to allow dynamic rounding modes,
I forgot to no longer hard-code FPSCR.FR = 0
openpower/isa/fpcvt.mdwn diff | blob | history
src/openpower/test/fmv_fcvt/fmv_fcvt.py diff | blob | history