MEM: Split SimpleTimingPort into PacketQueue and ports
authorAndreas Hansson <andreas.hansson@arm.com>
Thu, 22 Mar 2012 10:36:27 +0000 (06:36 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Thu, 22 Mar 2012 10:36:27 +0000 (06:36 -0400)
commitc2d2ea99e3efe13bc50d410e2eeae9dd6757e57f
tree5836cc125091b436dee3fbc32ef26e1eeed49a6c
parentfb395b56dd2432b862c550bad7b4bbe1f205ec59
MEM: Split SimpleTimingPort into PacketQueue and ports

This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).

As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.

The PioPort and MessagePort are cleaned up as part of the changes.

--HG--
rename : src/mem/tport.cc => src/mem/packet_queue.cc
rename : src/mem/tport.hh => src/mem/packet_queue.hh
17 files changed:
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/x86/intdev.cc
src/mem/SConscript
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache.hh
src/mem/cache/cache_impl.hh
src/mem/mport.hh
src/mem/packet_queue.cc [new file with mode: 0644]
src/mem/packet_queue.hh [new file with mode: 0644]
src/mem/physical.cc
src/mem/qport.hh [new file with mode: 0644]
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/tport.cc
src/mem/tport.hh